== Series Details == Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev6) URL : https://patchwork.freedesktop.org/series/103491/ State : warning == Summary == Error: dim checkpatch failed 0cf5770ce11c drm/i915: Relocate intel_crtc_dotclock() 8e214039c42f drm/i915: Shuffle some PLL code around 0a40c0aea05b drm/i915: Extract HAS_DOUBLE_BUFFERED_M_N() -:53: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #53: FILE: drivers/gpu/drm/i915/i915_drv.h:1255: +#define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) -:53: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #53: FILE: drivers/gpu/drm/i915/i915_drv.h:1255: +#define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) total: 0 errors, 1 warnings, 1 checks, 25 lines checked d135effc011e drm/i915/dsi: Extract {vlv, bxt}_get_pclk() 4cd472892736 drm/i915: Do .crtc_compute_clock() earlier 3f4eddf2ca58 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() 4cae9fa84b8b drm/i915: Feed the DPLL output freq back into crtc_state 27da5a8db7b3 drm/i915: Compute clocks earlier edee938717df drm/i915: Make M/N checks non-fuzzy 0358bca96699 drm/i915: Make all clock checks non-fuzzy e399283bacc7 drm/i915: Set active dpll early for icl+ 320064a4eba6 drm/i915: Nuke fastet state copy hacks e46e10fbf5a6 drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled 311d51a7485d drm/i915: Add intel_panel_highest_mode() ce21626434d0 drm/i915: Allow M/N change during fastset on bdw+ e27993638185 drm/i915: Use a fixed N value always c87c710ada27 drm/i915: Round TMDS clock to nearest
