From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
And with fastset made to not suck we can consider allowing
seameless M/N changes on eDP panels that support such things.
I've given that a quick test here on a TGL and it seemed to work
OK.
The rough parts:
- The DPLL stuff is kinda messy still, a lot of which is due to
the dpll_mgr vs. not depending on platform/output type. Maybe
it's finally time to start cleaning that mess up...
- the port_dpll[] stuff probably needs to be reworked at some
point to make a bit more sense
- fastboot I *think* should mostly keep working now that we
try to match the GOP/VBIOS M/N behaviour. FDI M/N vs. DPLL is
a bit of a challenge for the platforms where the encoder live
in the PCH, but I'm going to declare that as not so important
- DSI clock handling is snafu
- DP link computation policy might need a bit more work since we
may now consume more bandwidth than before on machines where
seamless M/N changes are possible
I also did a quick smoke test through the series on tgl and
snb in the hopes of keeping this at least mostly bisectable.
Changes in v2:
- bunch of stuff already merged
- a bit more refactoring to make things nicer
- Tweak the M/N rounding for fastboot
- don't mess with the DP link rate on platforms (pre-BDW)
where we haven't implemented seamsless M/N chages
Changes in v3:
- Attempt to get the VLV/BXT DSI stuff to pass CI :/
Ville Syrjälä (17):
drm/i915: Relocate intel_crtc_dotclock()
drm/i915: Shuffle some PLL code around
drm/i915: Extract HAS_DOUBLE_BUFFERED_M_N()
drm/i915/dsi: Extract {vlv,bxt}_get_pclk()
drm/i915: Do .crtc_compute_clock() earlier
drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
drm/i915: Feed the DPLL output freq back into crtc_state
drm/i915: Compute clocks earlier
drm/i915: Make M/N checks non-fuzzy
drm/i915: Make all clock checks non-fuzzy
drm/i915: Set active dpll early for icl+
drm/i915: Nuke fastet state copy hacks
drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not
enabled
drm/i915: Add intel_panel_highest_mode()
drm/i915: Allow M/N change during fastset on bdw+
drm/i915: Use a fixed N value always
drm/i915: Round TMDS clock to nearest
drivers/gpu/drm/i915/display/intel_crt.c | 3 +
drivers/gpu/drm/i915/display/intel_ddi.c | 22 --
drivers/gpu/drm/i915/display/intel_display.c | 199 +++++++----------
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 50 +++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 69 +++++-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 204 ++++++++++--------
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
.../drm/i915/display/intel_modeset_verify.c | 6 +-
drivers/gpu/drm/i915/display/intel_panel.c | 15 ++
drivers/gpu/drm/i915/display/intel_panel.h | 3 +
.../gpu/drm/i915/display/intel_pch_refclk.c | 10 +
.../gpu/drm/i915/display/intel_pch_refclk.h | 1 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 11 +-
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 141 +++++++-----
drivers/gpu/drm/i915/i915_drv.h | 2 +
19 files changed, 420 insertions(+), 326 deletions(-)
--
2.35.1
