On Mon, 20 Jun 2022, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > We have a couple of places that want to make distinction between > double buffered M/N registers vs. the split M1/N1+M2/N2 registers. > Add a helper for that. > > v2: Turn into a HAS_ macro (Jani) > > Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> #v1 > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> I'm fine with this, obviously, but also started wondering about the other direction [1]. BR, Jani. [1] https://patchwork.freedesktop.org/patch/msgid/dc7e02a24fc231ef0fa3c4e84c01ebf19d61de2f.1655748056.git.jani.nikula@xxxxxxxxx > --- > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > drivers/gpu/drm/i915/display/intel_dp.c | 3 +-- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > 3 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 6b549aadca13..0384af821ee5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5760,7 +5760,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_I(lane_count); > PIPE_CONF_CHECK_X(lane_lat_optim_mask); > > - if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { > + if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { > PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); > } else { > PIPE_CONF_CHECK_M_N(dp_m_n); > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index e0891b31f089..cf7e4e105891 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1868,8 +1868,7 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, > static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915, > enum transcoder cpu_transcoder) > { > - /* M1/N1 is double buffered */ > - if (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) > + if (HAS_DOUBLE_BUFFERED_M_N(i915)) > return true; > > return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index c22f29c3faa0..805ae6ca7486 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1252,6 +1252,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) > #define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) > > +#define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) > + > #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) > #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) > #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) -- Jani Nikula, Intel Open Source Graphics Center
