> -----Original Message----- > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Sent: Thursday, March 24, 2022 3:12 PM > To: Shankar, Uma <uma.shankar@xxxxxxxxx> > Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: Re: [v2] drm/i915/display: Extend DP HDR support to hsw+ > > On Thu, Mar 24, 2022 at 02:42:15PM +0530, Uma Shankar wrote: > > HSW+ platforms are able to send out HDR Metadata SDP DIP > > packet as GMP. Hence, extending the support for HDR on DP encoders for > > the same. > > > > v2: Limited to non eDP ports on hsw/bdw and removed it for lspcon as > > it is done separately (suggested by Ville) > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389 > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++---- > > 1 file changed, 6 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 9e19165fd175..09382b6133bc 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -4939,10 +4939,12 @@ intel_dp_add_properties(struct intel_dp *intel_dp, > struct drm_connector *connect > > intel_attach_dp_colorspace_property(connector); > > } > > > > - if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11) > > - drm_object_attach_property(&connector->base, > > - connector->dev- > >mode_config.hdr_output_metadata_property, > > - 0); > > + if (!intel_bios_is_lspcon_present(dev_priv, port)) > > + if (((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && > > + !intel_dp_is_edp(intel_dp)) || DISPLAY_VER(dev_priv) >= 9) > > s/is_edp/port==A/ Yeah missed to limit only for port A, will fix it. > I would put all of that into a helper (has_gamut_metadata_dip() or > something) to make it actually legible. Sure, will add a helper. Regards, Uma Shankar > > > + drm_object_attach_property(&connector->base, > > + connector->dev- > >mode_config.hdr_output_metadata_property, > > + 0); > > > > if (intel_dp_is_edp(intel_dp)) { > > u32 allowed_scalers; > > -- > > 2.25.1 > > -- > Ville Syrjälä > Intel
