On Wed, 23 Mar 2022 at 16:32, Christian König <christian.koenig@xxxxxxx> wrote: > > Am 23.03.22 um 16:24 schrieb Daniel Stone: > > On Wed, 23 Mar 2022 at 15:14, Alex Deucher <alexdeucher@xxxxxxxxx> wrote: > >> On Wed, Mar 23, 2022 at 11:04 AM Daniel Stone <daniel@xxxxxxxxxxxxx> wrote: > >>> That's not what anyone's saying here ... > >>> > >>> No-one's demanding AMD publish RTL, or internal design docs, or > >>> hardware specs, or URLs to JIRA tickets no-one can access. > >>> > >>> This is a large and invasive commit with pretty big ramifications; > >>> containing exactly two lines of commit message, one of which just > >>> duplicates the subject. > >>> > >>> It cannot be the case that it's completely impossible to provide any > >>> justification, background, or details, about this commit being made. > >>> Unless, of course, it's to fix a non-public security issue, that is > >>> reasonable justification for eliding some of the details. But then > >>> again, 'huge change which is very deliberately opaque' is a really > >>> good way to draw a lot of attention to the commit, and it would be > >>> better to provide more detail about the change to help it slip under > >>> the radar. > >>> > >>> If dri-devel@ isn't allowed to inquire about patches which are posted, > >>> then CCing the list is just a façade; might as well just do it all > >>> internally and periodically dump out pull requests. > >> I think we are in agreement. I think the withheld information > >> Christian was referring to was on another thread with Christian and > >> Paul discussing a workaround for a hardware bug: > >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.spinics.net%2Flists%2Famd-gfx%2Fmsg75908.html&data=04%7C01%7Cchristian.koenig%40amd.com%7C6a3f2815d83b4872577008da0ce1347a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637836458652370599%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=QtNB0XHMhTgH%2FNHMwF23Qn%2BgSdYyHJSenbpP%2FHG%2BkxE%3D&reserved=0 > > Right, that definitely seems like some crossed wires. I don't see > > anything wrong with that commit at all: the commit message and a > > comment notes that there is a hardware issue preventing Raven from > > being able to do TMZ+GTT, and the code does the very straightforward > > and obvious thing to ensure that on VCN 1.0, any TMZ buffer must be > > VRAM-placed. > > > > This one, on the other hand, is much less clear ... > > Yes, completely agree. I mean a good bunch of comments on commit > messages are certainly valid and we could improve them. > > But this patch here was worked on by both AMD and Intel developers. > Where both sides and I think even people from other companies perfectly > understands why, what, how etc... > > When now somebody comes along and asks for a whole explanation of the > context why we do it then that sounds really strange to me. Yeah gpus are using pages a lot more like the cpu (with bigger pages of benefit, but not required, hence the buddy allocator to coalesce them), and extremely funny contig allocations with bonkers requirements aren't needed anymore (which was the speciality of drm_mm.c). Hence why both i915 and amdgpu move over to this new buddy allocator for managing vram. I guess that could be added to the commit message, but also it's kinda well known - the i915 patches also didn't explain why we want to manage our vram with a buddy allocator (I think some of the earlier versions explained it a bit, but the version with ttm integration that landed didnt). But yeah the confusing comments about hiding stuff that somehow spilled over from other discussions into this didn't help :-/ -Daniel > Thanks for jumping in here, > Christian. > > > > > Cheers, > > Daniel > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
