On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Don't just mask off all the PSF GV points when SAGV gets disabled.
> This should in fact cause the Pcode to reject the request since
> at least one PSF point must remain enabled at all times.
Good point, however I think this is not the full fix:
BSpec says:
"At least one GV point of each type must always remain unmasked."
and
"The GV point of each type providing the highest bandwidth
for display must always remain unmasked."
So I guess we should then also choose thr PSF GV point with
the highest bandwidth as well.
Stan
>
> Cc: stable@xxxxxxxxxxxxxxx
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point support")
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index ad1564ca7269..adf58c58513b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -992,7 +992,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> * cause.
> */
> if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
> - allowed_points = BIT(max_bw_point);
> + allowed_points &= ADLS_PSF_PT_MASK;
> + allowed_points |= BIT(max_bw_point);
> drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
> max_bw_point);
> }
> --
> 2.34.1
>
