On Thu, Jun 20, 2013 at 10:14:36AM +0100, Chris Wilson wrote: > On Thu, Jun 20, 2013 at 11:17:16AM +0300, Ville Syrj?l? wrote: > > Assuming all the planes on a specific piece of hardware have the same > > pitch limits, I'd like the checks to be live in > > intel_framebuffer_init() so that the issue gets caught as early as > > possible. For stricter per-plane limits we obviously need the checks > > in update_plane. > > > > What I can gather from BSpec is this: > > gen2: linear/tiled 8k, (maybe DSPC tiled max 4k?) > > gen3: linear ?, tiled 8k > > gen4: linear ?, tiled 16k > > ctg: linear ?, tiled 16k > > ilk+: 32k all the way > > > > Looking at your patch you have 16k,32k,32k for the ?s in my list. > > Otherwise your numbers seem to agree with my findings. > > The only one I didn't check was the VLV addendum. My VLV doc says 16K for tiled. -- Ville Syrj?l? Intel OTC
