On Thu, Jun 20, 2013 at 10:14:36AM +0100, Chris Wilson wrote: > On Thu, Jun 20, 2013 at 11:17:16AM +0300, Ville Syrj?l? wrote: > > We already have a bit of pitch checking in intel_framebuffer_init(). > > In fact there's a FIXME about pre-ilk limits there. > > It looks tidier to fix that check. We still need to double check the > values though as the tiling mode is independent of the fb config and may > be changed by the user. True, some checking needs to be done after pinning. I guess we could have one function that has the checks, and just call it from both places. > > > Assuming all the planes on a specific piece of hardware have the same > > pitch limits, I'd like the checks to be live in > > intel_framebuffer_init() so that the issue gets caught as early as > > possible. For stricter per-plane limits we obviously need the checks > > in update_plane. > > > > What I can gather from BSpec is this: > > gen2: linear/tiled 8k, (maybe DSPC tiled max 4k?) > > gen3: linear ?, tiled 8k > > gen4: linear ?, tiled 16k > > ctg: linear ?, tiled 16k > > ilk+: 32k all the way > > > > Looking at your patch you have 16k,32k,32k for the ?s in my list. > > Otherwise your numbers seem to agree with my findings. > > The only one I didn't check was the VLV addendum. > > > So, to me it looks like all the planes do share the same limits (DSPC on > > gen2 might be a minor exception), so I think we could move all of these > > checks to intel_framebuffer_init(). > > Except for the rare cases where the limits may change between init and > set-base... > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre -- Ville Syrj?l? Intel OTC
