On Wed, May 29, 2013 at 09:43:05PM +0200, Daniel Vetter wrote:
> This was accidentally broken in the south error interrupt handling
> work:
>
> commit 8664281b64c457705db72fc60143d03827e75ca9
> Author: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Date: Fri Apr 12 17:57:57 2013 -0300
>
> drm/i915: report Gen5+ CPU and PCH FIFO underruns
>
> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Cc: Ben Widawsky <ben at bwidawsk.net>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Adding Imre since he's reviewed the offending patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_irq.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index da5c9ab..7c9264f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2610,6 +2610,9 @@ static void ibx_irq_postinstall(struct drm_device *dev)
> drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> u32 mask;
>
> + if (HAS_PCH_NOP(dev))
> + return;
> +
> if (HAS_PCH_IBX(dev)) {
> mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
> SDE_TRANSA_FIFO_UNDER | SDE_POISON;
> @@ -2619,9 +2622,6 @@ static void ibx_irq_postinstall(struct drm_device *dev)
> I915_WRITE(SERR_INT, I915_READ(SERR_INT));
> }
>
> - if (HAS_PCH_NOP(dev))
> - return;
> -
> I915_WRITE(SDEIIR, I915_READ(SDEIIR));
> I915_WRITE(SDEIMR, ~mask);
> }
> --
> 1.7.10.4
>
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
