On Fri, May 24, 2013 at 08:00:26PM +0300, Ville Syrj?l? wrote:
> On Fri, May 24, 2013 at 11:59:18AM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> >
> > On Haswell, whenever we change the sprites we need to completely
> > recalculate all the watermarks, because the sprites are one of the
> > parameters to the LP watermarks, so a change on the sprites may
> > trigger a change on which LP levels are enabled.
> >
> > So on this commit we store all the parameters we need to store for
> > proper recalculation of the Haswell WMs and then call
> > haswell_update_wm.
> >
> > Notice that for now our haswell_update_wm function is not really using
> > these parameters we're storing, but on the next commits we'll use
> > these parameters.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com>
First 2 patches merged to dinq, thanks. Although I do need to whine a bit
about how the state tracking in our sprite code seems to be bong-hits here
... ;-) But I guess Ville will tackle this with his plane config rework.
Cheers, Daniel
>
> > ---
> > drivers/gpu/drm/i915/intel_drv.h | 12 ++++++++++++
> > drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++++++++-
> > 2 files changed, 34 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 21427aa..57de0c1 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -326,6 +326,18 @@ struct intel_plane {
> > unsigned int crtc_w, crtc_h;
> > uint32_t src_x, src_y;
> > uint32_t src_w, src_h;
> > +
> > + /* Since we need to change the watermarks before/after
> > + * enabling/disabling the planes, we need to store the parameters here
> > + * as the other pieces of the struct may not reflect the values we want
> > + * for the watermark calculations. Currently only Haswell uses this.
> > + */
> > + struct {
> > + bool enable;
> > + uint8_t bytes_per_pixel;
> > + uint32_t horiz_pixels;
> > + } wm;
> > +
> > void (*update_plane)(struct drm_plane *plane,
> > struct drm_framebuffer *fb,
> > struct drm_i915_gem_object *obj,
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 3ebb8e9..0b61a0e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2118,6 +2118,26 @@ static void haswell_update_wm(struct drm_device *dev)
> > sandybridge_update_wm(dev);
> > }
> >
> > +static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
> > + uint32_t sprite_width, int pixel_size,
> > + bool enable)
> > +{
> > + struct drm_plane *plane;
> > +
> > + list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
> > + struct intel_plane *intel_plane = to_intel_plane(plane);
> > +
> > + if (intel_plane->pipe == pipe) {
> > + intel_plane->wm.enable = enable;
> > + intel_plane->wm.horiz_pixels = sprite_width + 1;
> > + intel_plane->wm.bytes_per_pixel = pixel_size;
> > + break;
> > + }
> > + }
> > +
> > + haswell_update_wm(dev);
> > +}
> > +
> > static bool
> > sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
> > uint32_t sprite_width, int pixel_size,
> > @@ -4635,7 +4655,8 @@ void intel_init_pm(struct drm_device *dev)
> > } else if (IS_HASWELL(dev)) {
> > if (I915_READ64(MCH_SSKPD)) {
> > dev_priv->display.update_wm = haswell_update_wm;
> > - dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
> > + dev_priv->display.update_sprite_wm =
> > + haswell_update_sprite_wm;
> > } else {
> > DRM_DEBUG_KMS("Failed to read display plane latency. "
> > "Disable CxSR\n");
> > --
> > 1.8.1.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrj?l?
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
