From: Paulo Zanoni <paulo.r.zanoni at intel.com> Hi This series is a new version of "drm/i915: replace snb_update_wm with haswell_update_wm on HSW". Ville asked to split the series into smaller patches, so here they are. I also implemented the other suggestions made by Ville. After this series, the only thing missing for correctness of the Haswell watermark register values will be to use the correct mode clock when calculating linetime watermarks. I had a patch for this, but Daniel suggested to wait until we merge "drm/i915: store adjust dotclock in adjustede_mode->clock". I can already see us reaching PC7 state with this series on eDP 1920x1080 with 138.78MHz pixel clock. Thanks, Paulo Paulo Zanoni (5): drm/i915: add "enable" argument to intel_update_sprite_watermarks drm/i915: add haswell_update_sprite_wm drm/i915: properly set HSW WM_PIPE registers drm/i915: properly set HSW WM_LP watermarks drm/i915: add support for 5/6 data buffer partitioning on Haswell drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_reg.h | 7 + drivers/gpu/drm/i915/intel_drv.h | 14 +- drivers/gpu/drm/i915/intel_pm.c | 588 ++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_sprite.c | 8 +- 5 files changed, 593 insertions(+), 27 deletions(-) -- 1.8.1.2
