| Series: | drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) |
| URL: | https://patchwork.freedesktop.org/series/95948/ |
| State: | success |
| Details: | https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/index.html |
CI Bug Log - changes from CI_DRM_10753 -> Patchwork_21374
Summary
SUCCESS
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/index.html
Known issues
Here are the changes found in Patchwork_21374 that come from known issues:
IGT changes
Issues hit
-
igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> SKIP (fdo#109271) +17 similar issues
-
igt@gem_exec_suspend@basic-s0:
Possible fixes
- igt@i915_selftest@live@hangcheck:
- fi-snb-2600: INCOMPLETE (i915#3921) -> PASS
Participating hosts (39 -> 37)
Missing (2): fi-bsw-cyan bat-dg1-6
Build changes
- Linux: CI_DRM_10753 -> Patchwork_21374
CI-20190529: 20190529
CI_DRM_10753: 57c1bcf63565db8d65783364c632a04a44bbd616 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6254: 51792e987da03ba2a6faf5857c12f1d173c87def @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21374: d94f0647dd7812e0f536f8199860568c6a0d2cf9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d94f0647dd78 drm/i915/dp: Sanitize link common rate array lookups
f2bd5e3e941b drm/i915/dp: Sanitize sink rate DPCD register values
66b542816538 drm/i915/dp: Ensure sink/link max lane count values are always valid
ef437e0c551b drm/i915/dp: Ensure max link params are always valid
4de2ca096081 drm/i915/dp: Ensure sink rate values are always valid
8f1a6421dfe5 drm/i915/dp: Skip the HW readout of DPCD on disabled encoders
