This patchset fixes a few issues, related to invalid accesses from the intel_dp->common_rates[] array and in general the link rate, lane count parameters being invalid until a valid DPCD is read from the sink. One issue in intel_dp_sync_state() was caught by the CONFIG_UBSAN feature. The first 3 patches are also needed for stable kernels. Cc: José Roberto de Souza <jose.souza@xxxxxxxxx> Cc: Jani Nikula <jani.nikula@xxxxxxxxx> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Imre Deak (6): drm/i915/dp: Skip the HW readout of DPCD on disabled encoders drm/i915/dp: Ensure sink rate values are always valid drm/i915/dp: Ensure max link params are always valid drm/i915/dp: Ensure sink/link max lane count values are always valid drm/i915/dp: Sanitize sink rate DPCD register values drm/i915/dp: Sanitize link common rate array lookups .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 127 ++++++++++++++---- 2 files changed, 101 insertions(+), 28 deletions(-) -- 2.27.0
