| Series: | drm/i915/dp: dp 2.0 enabling prep work |
| URL: | https://patchwork.freedesktop.org/series/93800/ |
| State: | success |
| Details: | https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20850/index.html |
CI Bug Log - changes from CI_DRM_10497 -> Patchwork_20850
Summary
SUCCESS
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20850/index.html
Known issues
Here are the changes found in Patchwork_20850 that come from known issues:
IGT changes
Issues hit
-
igt@amdgpu/amd_basic@cs-gfx:
-
fi-rkl-guc: NOTRUN -> SKIP (fdo#109315) +17 similar issues
-
fi-kbl-soraka: NOTRUN -> SKIP (fdo#109271) +6 similar issues
-
-
igt@runner@aborted:
Possible fixes
- igt@core_hotunplug@unbind-rebind:
- fi-rkl-guc: DMESG-WARN (i915#3925) -> PASS
Warnings
- igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: FAIL (i915#579) -> SKIP (fdo#109271)
Participating hosts (34 -> 33)
Missing (1): fi-bsw-cyan
Build changes
- Linux: CI_DRM_10497 -> Patchwork_20850
CI-20190529: 20190529
CI_DRM_10497: c50a8ea72915f1e3972d011690a423bafbee7a58 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6178: 146260200f9a6d4536e48a195e2ab49a07d4f0c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20850: f619e6bfa217e2f33dfb31e0da1262cae8c9209f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f619e6bfa217 drm/i915/dg2: update link training for 128b/132b
44526b8ce97b drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b
73b7a835f7b3 drm/i915/dg2: use 128b/132b transcoder DDI mode
753442fe1e74 drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0
76465b4d3708 drm/i915/dp: select 128b/132b channel encoding for UHBR rates
7d3f86063b7b drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates
9cf6be09b318 drm/i915/dp: add max data rate calculation for UHBR rates
310bd160b5df drm/i915/dg2: add DG2 UHBR source rates
09dd0b1c53f5 drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW
2ae1f5cd9112 drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode
bd393efa3f8d drm/i915/dg2: add TRANS_DP2_CTL register definition
4d03932add3c drm/i915/dp: read sink UHBR rates
2c801bbdc46b drm/i915/dp: use actual link rate values in struct link_config_limits
348fff506827 drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
176cd12c2a2e drm/dp: add LTTPR DP 2.0 DPCD addresses
15972d4824f6 drm/dp: use more of the extended receiver cap
098494421cf3 drm/dp: add DP 2.0 UHBR link rate and bw code conversions
