VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.
v2:
- Check for dsc enable and slice count ==1 then allow to
double confirm min cdclk value.
- Add more checking in dsi_dsc_compute_config() to avoid
crtc_clock exceeds dev_priv->max_cdclk_freq.
Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
Cc: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
Cc: Cooper Chiou <cooper.chiou@xxxxxxxxx>
Cc: William Tseng <william.tseng@xxxxxxxxx>
Signed-off-by: Lee Shawn C <shawn.c.lee@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++++++++
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 60413bbf565f..c51ba3b9051e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1592,6 +1592,8 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
bool use_dsc;
int ret;
@@ -1612,6 +1614,22 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
/* FIXME: initialize from VBT */
vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+ /*
+ * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
+ * is greater than the maximum Cdclock and if slice count is even
+ * then we need to use 2 VDSC instances.
+ */
+ if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
+ crtc_state->bigjoiner) {
+ if (crtc_state->dsc.slice_count < 2) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Cannot split stream to use 2 VDSC instances\n");
+ return -EINVAL;
+ }
+
+ crtc_state->dsc.dsc_split = true;
+ }
+
ret = intel_dsc_compute_params(encoder, crtc_state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 71067a62264d..3e09f6370d27 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2159,6 +2159,16 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
+ /*
+ * VDSC engine can process only 1 pixel per Cd clock.
+ * In case VDSC is used and max slice count == 1,
+ * max supported pixel clock should be 100% of CD clock.
+ * Then do min_cdclk and pixel clock comparison to get cdclk.
+ */
+ if (crtc_state->dsc.compression_enable &&
+ crtc_state->dsc.slice_count == 1)
+ min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+
/*
* HACK. Currently for TGL platforms we calculate
* min_cdclk initially based on pixel_rate divided
--
2.17.1
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