v2: - Check for dsc enable and slice count ==1 then allow to double confirm min cdclk value. - Add more checking in dsi_dsc_compute_config() to avoid crtc_clock exceeds dev_priv->max_cdclk_freq. Lee Shawn C (5): drm/i915/dsi: send correct gpio_number on gen11 platform drm/i915/jsl: program DSI panel GPIOs drm/i915/dsi: wait for header and payload credit available drm/i915/dsi: refine send MIPI DCS command sequence drm/i915: Get proper min cdclk if vDSC enabled drivers/gpu/drm/i915/display/icl_dsi.c | 68 ++++++++++++-------- drivers/gpu/drm/i915/display/intel_cdclk.c | 10 +++ drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 46 ++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 10 +++ 4 files changed, 106 insertions(+), 28 deletions(-) -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
