On Wed, Apr 24, 2013 at 02:23:20PM +0300, Ville Syrj?l? wrote:
> On Fri, Apr 19, 2013 at 11:24:41AM +0200, Daniel Vetter wrote:
> > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++--
> > 1 file changed, 18 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 7cb1abf..b7774c1 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5766,9 +5766,13 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> > if (!(tmp & PIPECONF_ENABLE))
> > return false;
> >
> > - if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
> > + if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> > pipe_config->has_pch_encoder = true;
> >
> > + tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
> > + pipe_config->fdi_lanes = ((tmp >> 19) & 0x3) + 1;
>
> Should we add names for the shifts/mask values? Or maybe we have them
> already...
It's copy&pasta from where we store the lane counts, I can respin the
patch and de-magic both places.
> And should we check the TX side too and make sure both sides agree on
> the number of lanes?
Presumably when the RX is enabled, there's a TX for it. And TX state is a
bit more messy, especially on haswell. Hence just RX. We could add some
checks in the crtc disable code I guess to sanity check TX settings before
disabling things (so that we at least notice broken things), but I've
figured the black screen would be cause enough for a bug report. So imo ok
if we delay adding that until there's a real need for it.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
