From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Let's just store the dbuf slice information as a bitmask
in the device info. Makes life a little easier later.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++--
drivers/gpu/drm/i915/i915_pci.c | 6 +++---
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++----
drivers/gpu/drm/i915/intel_pm.h | 1 +
5 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0e433a0e1fce..0435103082eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4777,7 +4777,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
+ int num_slices = intel_dbuf_num_slices(dev_priv);
struct i915_power_domains *power_domains = &dev_priv->power_domains;
enum dbuf_slice slice;
@@ -4825,7 +4825,7 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
{
- int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
+ int num_slices = intel_dbuf_num_slices(dev_priv);
enum dbuf_slice slice;
for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 981d12702c49..15eb078fe6bb 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -648,7 +648,7 @@ static const struct intel_device_info chv_info = {
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
- .dbuf.num_slices = 1
+ .dbuf.slice_mask = BIT(DBUF_S1)
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -683,7 +683,7 @@ static const struct intel_device_info skl_gt4_info = {
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
- .dbuf.num_slices = 1, \
+ .dbuf.slice_mask = BIT(DBUF_S1), \
.display.has_hotplug = 1, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -831,7 +831,7 @@ static const struct intel_device_info cnl_info = {
}, \
GEN(11), \
.dbuf.size = 2048, \
- .dbuf.num_slices = 2, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 74591e4f9c44..6aefe4fde197 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -198,7 +198,7 @@ struct intel_device_info {
struct {
u16 size; /* in blocks */
- u8 num_slices;
+ u8 slice_mask;
} dbuf;
/* Register offsets for the various display pipes and transcoders */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8d6ee5ad761e..88eb54241b9f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3637,7 +3637,7 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
{
int i;
- int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
+ int num_slices = intel_dbuf_num_slices(dev_priv);
u8 enabled_slices_mask = 0;
for (i = 0; i < num_slices; i++) {
@@ -4033,10 +4033,15 @@ static int intel_dbuf_size(struct drm_i915_private *dev_priv)
return INTEL_INFO(dev_priv)->dbuf.size;
}
+int intel_dbuf_num_slices(struct drm_i915_private *dev_priv)
+{
+ return hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
+}
+
static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
{
return intel_dbuf_size(dev_priv) /
- INTEL_INFO(dev_priv)->dbuf.num_slices;
+ intel_dbuf_num_slices(dev_priv);
}
static void
@@ -4063,7 +4068,7 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
{
u32 slice_mask = 0;
u16 ddb_size = intel_dbuf_size(dev_priv);
- int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
+ int num_slices = intel_dbuf_num_slices(dev_priv);
u16 slice_size = ddb_size / num_slices;
u16 start_slice;
u16 end_slice;
@@ -5821,7 +5826,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
"Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n",
old_dbuf_state->enabled_slices,
new_dbuf_state->enabled_slices,
- INTEL_INFO(dev_priv)->dbuf.num_slices);
+ intel_dbuf_num_slices(dev_priv));
}
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 669c8d505677..7dc11dec8984 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -38,6 +38,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
+int intel_dbuf_num_slices(struct drm_i915_private *dev_priv);
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
--
2.26.3
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