> -----Original Message-----
> From: Nikula, Jani <jani.nikula@xxxxxxxxx>
> Sent: Tuesday, March 2, 2021 3:55 PM
> To: Shankar, Uma <uma.shankar@xxxxxxxxx>; intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Varide, Nischal <nischal.varide@xxxxxxxxx>; Ville Syrjälä
> <ville.syrjala@xxxxxxxxxxxxxxx>
> Subject: RE: [PATCH v3 6/9] drm/i915/mso: add splitter state readout for
> platforms that support it
>
> On Mon, 22 Feb 2021, Jani Nikula <jani.nikula@xxxxxxxxx> wrote:
> > On Mon, 22 Feb 2021, "Shankar, Uma" <uma.shankar@xxxxxxxxx> wrote:
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> index 71611b596c88..5564db512d22 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> @@ -1161,6 +1161,13 @@ struct intel_crtc_state {
> >>> u8 pipeline_full;
> >>> u16 flipline, vmin, vmax;
> >>> } vrr;
> >>> +
> >>> + /* Stream Splitter for eDP MSO */
> >>> + struct {
> >>> + bool enable;
> >>> + u8 link_count;
> >>> + u8 pixel_overlap;
> >>> + } splitter;
> >>
> >> For DSI which also has this in common along with MSO, may be we can
> >> take these link_count and pixel_overlap out of splitter which is more
> >> of a MSO feature. Thoughts ?
> >
> > Ville suggested the same I think.
>
> Coming back to this. DSI does not actually use crtc state for this currently. But it
> does use the display stream splitter. The register is different, but the functionality is
> roughly the same.
>
> I suggest we keep the "splitter" substruct as above, and convert DSI code to use it in
> follow-up.
>
> In early versions of the patch the substruct was called "mso"; I think "splitter" is
> better, and captures both MSO and DSI cases.
>
> I'll send v4 with the other suggested changes.
Makes sense, I am ok with this.
Regards,
Uma Shankar
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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