On Wed, Feb 10, 2021 at 06:33:20AM +0200, Gupta, Anshuman wrote: > > On Tue, 2021-02-02 at 18:14 +0200, Imre Deak wrote: > > > > > > BSpec says about this WA for both ICL and TGL: > > > """ > > > Display driver should set and clear register offset 0xC2000 bit #7 as > > > last step in programming south display registers in preparation for > > > entering S0ix state, or set 0xC2000 bit #7 on S0ix entry and clear it > > > on S0ix exit. > > > > > > """ > > > > > > This means to me the WA is only relevant for S0ix and we can implement > > > it by setting/clearing 0xC2000 bit #7 right before entering/right > > > after exiting S0ix. This is done atm on PCH_ICP..PCH_MCC in > > > intel_display_power_suspend_late()/intel_display_power_resume_early(), > > > so I'd move the WA for all platforms there. > > > > > > I assume the current code in irq_reset() was the first alternative to > > > implement the WA, but it wasn't enough. Not sure why, maybe there is a > > > south display register access after irq_reset() during suspend. Adding > > > Anshuman for an idea on that. > > > > > > > Poking Anshuman here, is there any update on this? I'm looking to push these > > patches forward as some of Red Hat's hardware partners are very eager for this > > to get upstream asap as we're running out of time from our end. If you can > > answer this, I can handle respinning this patch as needed. > > My sincere apology, I had missed this thread. We have decided to keep > the alternative WA i.e setting/clearing 0xC2000 bit #7 before > entering after exiting s0ix to fix the deeper s0ix power consumption > issues on ICL_PCH families platforms. This alternative WA was added > to B.Spec on our request. But on TGL_PCH first alternative WA logic > i.e in irq_reset() was working to attain deeper s0ix residencies so > we haven't changed that. Ok, thanks for the explanation. For now I'd just ask to add a TODO: in this patch to check if the WA can be applied in the s0ix suspend/resume handlers as on earlier platforms and whether the WA is also needed for runtime s/r. --Imre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
