..snip.. (comments down below) On Tue, 2021-02-02 at 18:14 +0200, Imre Deak wrote: > > BSpec says about this WA for both ICL and TGL: > """ > Display driver should set and clear register offset 0xC2000 bit #7 as > last step in programming south display registers in preparation for > entering S0ix state, or set 0xC2000 bit #7 on S0ix entry and clear it on > S0ix exit. > > """ > > This means to me the WA is only relevant for S0ix and we can implement > it by setting/clearing 0xC2000 bit #7 right before entering/right after > exiting S0ix. This is done atm on PCH_ICP..PCH_MCC in > intel_display_power_suspend_late()/intel_display_power_resume_early(), > so I'd move the WA for all platforms there. > > I assume the current code in irq_reset() was the first alternative to > implement the WA, but it wasn't enough. Not sure why, maybe there is a > south display register access after irq_reset() during suspend. Adding > Anshuman for an idea on that. > Poking Anshuman here, is there any update on this? I'm looking to push these patches forward as some of Red Hat's hardware partners are very eager for this to get upstream asap as we're running out of time from our end. If you can answer this, I can handle respinning this patch as needed. > --Imre > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > -- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite! _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
