> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville > Syrjala > Sent: Thursday, July 16, 2020 10:21 AM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: [PATCH 11/14] drm/i915: Sort CFL PCI IDs > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Sort the CFL PCI IDs numerically. Some order seems better than > randomness. > > Cc: Alexei Podtelezhnikov <apodtele@xxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> > --- > include/drm/i915_pciids.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index > 2d36cbce0ac0..c48c2b76aa7d 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -497,8 +497,8 @@ > INTEL_VGA_DEVICE(0x3E9C, info) > > #define INTEL_CFL_H_GT2_IDS(info) \ > - INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ > - INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ > + INTEL_VGA_DEVICE(0x3E94, info), /* Halo GT2 */ \ > + INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */ > > /* CFL U GT2 */ > #define INTEL_CFL_U_GT2_IDS(info) \ > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
