On 10/09/2020 14:31, Tom Murphy wrote:
> This patch series fixes the issue I was having. I tested it with my
> patch set ("[PATCH V2 0/5] Convert the intel iommu driver to the
> dma-iommu api") applied, excluding the last patch in that series which
> disables the coalescing.
>
> So once your patch set is merged we should be good to convert the
> intel iommu driver to the dma-iommu api
There appears to be an issue on Ivybridge, which is an older platforms, which manifests like this:
<3> [209.526605] DMAR: intel_iommu_map: iommu width (39) is not sufficient for the mapped address (ffff008000)
Relevant iommu boot related messages are:
<6>[ 0.184234] DMAR: Host address width 36
<6>[ 0.184245] DMAR: DRHD base: 0x000000fed90000 flags: 0x0
<6>[ 0.184288] DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap c0000020e60262 ecap f0101a
<6>[ 0.184308] DMAR: DRHD base: 0x000000fed91000 flags: 0x1
<6>[ 0.184337] DMAR: dmar1: reg_base_addr fed91000 ver 1:0 cap c9008020660262 ecap f0105a
<6>[ 0.184357] DMAR: RMRR base: 0x000000d8d28000 end: 0x000000d8d46fff
<6>[ 0.184377] DMAR: RMRR base: 0x000000db000000 end: 0x000000df1fffff
<6>[ 0.184398] DMAR-IR: IOAPIC id 2 under DRHD base 0xfed91000 IOMMU 1
<6>[ 0.184414] DMAR-IR: HPET id 0 under DRHD base 0xfed91000
<6>[ 0.184428] DMAR-IR: Queued invalidation will be enabled to support x2apic and Intr-remapping.
<6>[ 0.185173] DMAR-IR: Enabled IRQ remapping in x2apic mode
<6>[ 0.878934] DMAR: No ATSR found
<6>[ 0.878966] DMAR: dmar0: Using Queued invalidation
<6>[ 0.879007] DMAR: dmar1: Using Queued invalidation
<6>[ 0.915032] DMAR: Intel(R) Virtualization Technology for Directed I/O
<6>[ 0.915060] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
<6>[ 0.915084] software IO TLB: mapped [mem 0xc80d4000-0xcc0d4000] (64MB)
Full boot log at https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7054/fi-ivb-3770/boot0.txt, failures at https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7054/fi-ivb-3770/igt@i915_selftest@live@xxxxxxxx.
I suspect this has to be about the dma-iommu conversion itself and not anything i915 is doing incorrectly? Something in the new mapping code not respecting the iommu width limitation? (To be clear these results are with the "[PATCH V2 0/5] Convert the intel iommu driver to the dma-iommu api" series applied, minus the not coalescing patch.)
Regards,
Tvrtko
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