From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> There are incoming improvements to Intel IOMMU code to allow sg table coalescing on map operations. We do not handle that well (we assume 1:1 between backing store and DMA mapped entries) so this series is an attempt to improve this area and get ready for those changes. Tvrtko Ursulin (2): drm/i915: Fix DMA mapped scatterlist walks drm/i915: Fix DMA mapped scatterlist lookup drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 ++ drivers/gpu/drm/i915/gem/i915_gem_object.h | 20 +++++++++++++++++- .../gpu/drm/i915/gem/i915_gem_object_types.h | 17 ++++++++------- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 21 ++++++++++++------- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 6 +++--- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 17 ++++++++------- drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++-- drivers/gpu/drm/i915/gt/intel_gtt.h | 2 +- drivers/gpu/drm/i915/i915_scatterlist.h | 17 +++++++++++---- 9 files changed, 73 insertions(+), 33 deletions(-) -- 2.25.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
