On Sun, Aug 30, 2020 at 02:57:46PM +0200, Hans de Goede wrote: > The pwm-crc code is using 2 different enable bits: > 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) > 2. bit 0 of the BACKLIGHT_EN register > > The BACKLIGHT_EN register at address 0x51 really controls a separate > output-only GPIO which is earmarked to be used as output connected to the > backlight-enable pin for LCD panels, this GPO is part of the PMIC's > "Display Panel Control Block." . This pin should probably be moved over > to a GPIO provider driver (and consumers modified accordingly), but that > is something for an(other) patch. > > Enabling / disabling the actual PWM output is controlled by the > PWM_OUTPUT_ENABLE bit of the PWM0_CLK_DIV register. > > As the comment in the old code already indicates we must disable the PWM > before we can change the clock divider. But the crc_pwm_disable() and > crc_pwm_enable() calls the old code make for this only change the > BACKLIGHT_EN register; and the value of that register does not matter for > changing the period / the divider. What does matter is that the > PWM_OUTPUT_ENABLE bit must be cleared before a new value can be written. > > This commit modifies crc_pwm_config() to clear PWM_OUTPUT_ENABLE instead > when changing the period, so that period changes actually work. > > Note this fix will cause a significant behavior change on some devices > using the CRC PWM output to drive their backlight. Before the PWM would > always run with the output frequency configured by the BIOS at boot, now > the period time specified by the i915 driver will actually be honored. > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> > Signed-off-by: Hans de Goede <hdegoede@xxxxxxxxxx> > --- > drivers/pwm/pwm-crc.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) Acked-by: Thierry Reding <thierry.reding@xxxxxxxxx>
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