On Fri, Jul 24, 2020 at 02:38:58PM -0700, Lucas De Marchi wrote:
> DG1 has a new MOCS table. We still use the old definition of the table,
> but as for any dgfx card it doesn't contain the control_value values
> (these values don't matter as we won't program them).
>
> Bspec: 45101
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
Matches the bspec
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
I do notice that the general comment farther up the file says "The last
two entries are reserved by the hardware." --- I wonder if we should
change that to "the last few" since DG1 technically has four reserved
entries instead of just two.
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++++++++++++++++++++++++++-
> 1 file changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 632e08a4592b..7217c6e2087c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -280,6 +280,39 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
> GEN11_MOCS_ENTRIES
> };
>
> +static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
> + /* Error */
> + MOCS_ENTRY(0, 0, L3_0_DIRECT),
> +
> + /* UC */
> + MOCS_ENTRY(1, 0, L3_1_UC),
> +
> + /* Reserved */
> + MOCS_ENTRY(2, 0, L3_0_DIRECT),
> + MOCS_ENTRY(3, 0, L3_0_DIRECT),
> + MOCS_ENTRY(4, 0, L3_0_DIRECT),
> +
> + /* WB - L3 */
> + MOCS_ENTRY(5, 0, L3_3_WB),
> + /* WB - L3 50% */
> + MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
> + /* WB - L3 25% */
> + MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
> + /* WB - L3 12.5% */
> + MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
> +
> + /* HDC:L1 + L3 */
> + MOCS_ENTRY(48, 0, L3_3_WB),
> + /* HDC:L1 */
> + MOCS_ENTRY(49, 0, L3_1_UC),
> +
> + /* HW Reserved */
> + MOCS_ENTRY(60, 0, L3_1_UC),
> + MOCS_ENTRY(61, 0, L3_1_UC),
> + MOCS_ENTRY(62, 0, L3_1_UC),
> + MOCS_ENTRY(63, 0, L3_1_UC),
> +};
> +
> enum {
> HAS_GLOBAL_MOCS = BIT(0),
> HAS_ENGINE_MOCS = BIT(1),
> @@ -306,7 +339,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> {
> unsigned int flags;
>
> - if (INTEL_GEN(i915) >= 12) {
> + if (IS_DG1(i915)) {
> + table->size = ARRAY_SIZE(dg1_mocs_table);
> + table->table = dg1_mocs_table;
> + table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> + } else if (INTEL_GEN(i915) >= 12) {
> table->size = ARRAY_SIZE(tgl_mocs_table);
> table->table = tgl_mocs_table;
> table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> --
> 2.26.2
>
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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