v4:
- Remove already applied patches and rebase the rest
- Add new workarounds
- Add change to DMC_DEBUG register
v3:
- Make sure we don't bind the driver to the device while the driver is
not complete. This should unblock us to have these basic patches
merged so the next parts can be developed/refactored/implemented,
particularly related to lmem.
When we have these patches applied and lmem part working for at least
a display-only driver we can make it bind again. This guarantees we
don't regress.
- Remove most of the RKL patches. The only one I'm still carrying is the
one for WAs as they are very similar to the ones for DG1.
Particularly the patch for PLL on RKL was making CI for this series to
fail, so untangle both and let them both continue the review process
in parallel.
v2:
- Remove some wrong/unneeded patches
- Collect R-b
- Rebase
As in previous version, the RKL patches are here only for completeness
and avoid future conflicts, not to be reviewed/applied.
Original cover:
DG1 is a gen12 dgfx platform. This is the first batch of patches to
support it. It also depends on some in-flight patches adding RKL. In
order for this series to be compiled, I'm including them here.
While converting some of these patches to the current
intel_uncore/intel_de APIs I thought it could be useful to return the
previous value. The patch for that is included here, but I ended up
not using and it can be dropped if there is no interest.
Aditya Swarup (4):
drm/i915/dg1: Add DPLL macros for DG1
drm/i915/dg1: Add and setup DPLLs for DG1
drm/i915/dg1: Enable DPLL for DG1
drm/i915/dg1: Enable first 2 ports for DG1
Anshuman Gupta (2):
drm/i915/dg1: DG1 does not support DC6
drm/i915/dg1: Change DMC_DEBUG{1,2} registers
Clinton A Taylor (1):
drm/i915/dg1: invert HPD pins
Lucas De Marchi (5):
drm/i915/dg1: Define MOCS table for DG1
drm/i915/dg1: add hpd interrupt handling
drm/i915/dg1: gmbus pin mapping
drm/i915/dg1: map/unmap pll clocks
drm/i915/dg1: enable PORT C/D aka D/E
Matt Atwood (1):
drm/i915/dg1: Load DMC
Matt Roper (6):
drm/i915/dg1: Initialize RAWCLK properly
drm/i915/dg1: Wait for pcode/uncore handshake at startup
drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
drm/i915/dg1: Update comp master/slave relationships for PHYs
drm/i915/dg1: Update voltage swing tables for DP
drm/i915/dg1: provide port/phy mapping for vbt
Stuart Summers (1):
drm/i915/dg1: Add initial DG1 workarounds
Uma Shankar (1):
drm/i915/dg1: Add DG1 power wells
Venkata Sandeep Dhanalakota (1):
drm/i915/dg1: Increase mmio size to 4MB
drivers/gpu/drm/i915/display/intel_bios.c | 12 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +-
.../gpu/drm/i915/display/intel_combo_phy.c | 7 +-
drivers/gpu/drm/i915/display/intel_csr.c | 19 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 126 ++++++++++-
drivers/gpu/drm/i915/display/intel_display.c | 46 +++-
.../drm/i915/display/intel_display_debugfs.c | 9 +-
.../drm/i915/display/intel_display_power.c | 211 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 71 ++++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 ++
drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +-
drivers/gpu/drm/i915/display/intel_hotplug.c | 3 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 101 +++++++--
drivers/gpu/drm/i915/i915_drv.c | 3 +
drivers/gpu/drm/i915/i915_irq.c | 66 +++++-
drivers/gpu/drm/i915/i915_pci.c | 2 +
drivers/gpu/drm/i915/i915_reg.h | 63 +++++-
drivers/gpu/drm/i915/intel_pm.c | 17 +-
drivers/gpu/drm/i915/intel_sideband.c | 15 ++
drivers/gpu/drm/i915/intel_sideband.h | 2 +
drivers/gpu/drm/i915/intel_uncore.c | 4 +
24 files changed, 800 insertions(+), 77 deletions(-)
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
