On 01/07/2020 00:27, Dave Airlie wrote:
On Sat, 27 Jun 2020 at 03:17, Daniele Ceraolo Spurio
<daniele.ceraolospurio@xxxxxxxxx> wrote:
On 6/26/20 12:14 AM, Lucas De Marchi wrote:
Cc Matt and Daniele
On Thu, Jun 25, 2020 at 9:38 PM Dave Airlie <airlied@xxxxxxxxx> wrote:
I can't figure this out easily so I'd thought I'd just ask, but does
DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of
We'd need to go via lmem since there's no mappable aperture. There are
a few patches in tree for that
(see e.g. 54b512cd7a6d ("drm/i915: do not map aperture if it is not
available.")) but more missing.
To clarify, although the legacy aperture mapping that allowed the CPU to
access memory via the GGTT for swizzling is gone, VRAM/LMEM is still
cpu-mappable via pci bar.
Will leave the questions about possible trashing to Matt as he's more
familiar than me with how this works.
Matt?
Is DG1 assuming we can get 64-bit BARs always and the CPU will have
access to the complete VRAM? or is there any ideas about what happens
in those situations where 64-bit BARs aren't available and there is
memory pressure on the PCI BAR space.
With other discrete GPUs we've got lots of things like visible VRAM
limitations, writing page tables with GPU hw instead of from the CPU,
having mapping bring things into the visible area, so you can stream
something into VRAM, but then it'll migrated to non-visible area if
it's unmapped and there is memory pressure.
Yes, we just assume that LMEM size == LMEMBAR size, where the whole
thing is 1:1 mapped and CPU visible. We don't currently have the concept
of CPU visible/non-visible LMEM.
Dave.
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