On Fri, Jun 26, 2020 at 01:16:42AM +0300, Ville Syrjälä wrote:
> On Thu, Jun 25, 2020 at 03:04:33PM -0700, Manasi Navare wrote:
> > On Fri, Jun 26, 2020 at 12:28:53AM +0300, Ville Syrjälä wrote:
> > > On Wed, Jun 24, 2020 at 03:11:08PM -0700, Manasi Navare wrote:
> > > > Based on the platform, Bspec expects us to wait or poll with
> > > > timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active
> > > > after enabling DDI_BUF_CTL.
> > > >
> > > > v3:
> > > > * Add a new function _active for DDI BUF CTL to be non idle (Ville)
> > > > v2:
> > > > * Based on platform, fixed delay or poll (Ville)
> > > > * Use a helper to do this (Imre, Ville)
> > > >
> > > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > > > Cc: Imre Deak <imre.deak@xxxxxxxxx>
> > > > Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++-
> > > > 1 file changed, 15 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > index 7d5c8ab88fc4..ff6b1e9d1b4e 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> > > > port_name(port));
> > > > }
> > > >
> > > > +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
> > > > + enum port port)
> > > > +{
> > > > + if (INTEL_GEN(dev_priv) <= 9) {
> > >
> > > Didn't we want the poll approach for glk+?
> >
> > Actually in the bspec I only see Gen10+ has a 500usecs timeout
>
> glk has (mostly) gen10 display.
>
> Defacto standard form to write that test is
> 'GEN < 10 && !IS_GLK'.
Okay will update this and send in the next rev
Manasi
>
> >
> > Manasi
> > >
> > > > + usleep_range(600, 1000);
> > > > + return;
> > > > + }
> > > > +
> > > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > > > + DDI_BUF_IS_IDLE), 600))
> > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
> > > > + port_name(port));
> > > > +}
> > > > +
> > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> > > > {
> > > > switch (pll->info->id) {
> > > > @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> > > > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > > >
> > > > - udelay(600);
> > > > + intel_wait_ddi_buf_active(dev_priv, port);
> > >
> > > Missed the FDI case.
> > >
> > > Also we're still missing this for HDMI, on icl+ I think? Can't quite
> > > remember if that was where the spec started to demand it.
> > >
> > > > }
> > > >
> > > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
> > > > --
> > > > 2.19.1
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
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