As we rewrite the batches on the fly to implement the non-preemptible lock, we need to tell Tigerlake to read the batch afresh each time. Amusingly, the disable is a part of an arb-check, so we have to be careful not to include the arbitration point inside our unpreemptible loop. Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> --- tests/i915/gem_exec_balancer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c index 026f8347e..0e3b52900 100644 --- a/tests/i915/gem_exec_balancer.c +++ b/tests/i915/gem_exec_balancer.c @@ -1350,6 +1350,11 @@ static void __bonded_dual(int i915, *out = cycles; } +static uint32_t preparser_disable(void) +{ + return 0x5 << 23 | 1 << 8 | 1; /* preparser masked disable */ +} + static uint32_t sync_from(int i915, uint32_t addr, uint32_t target) { uint32_t handle = gem_create(i915, 4096); @@ -1363,14 +1368,14 @@ static uint32_t sync_from(int i915, uint32_t addr, uint32_t target) *cs++ = 0; *cs++ = 0; - *cs++ = MI_NOOP; + *cs++ = preparser_disable(); *cs++ = MI_NOOP; *cs++ = MI_NOOP; *cs++ = MI_NOOP; /* wait for them to cancel us */ *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; - *cs++ = addr + 16; + *cs++ = addr + 24; *cs++ = 0; /* self-heal */ @@ -1393,14 +1398,14 @@ static uint32_t sync_to(int i915, uint32_t addr, uint32_t target) cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); - *cs++ = MI_NOOP; + *cs++ = preparser_disable(); *cs++ = MI_NOOP; *cs++ = MI_NOOP; *cs++ = MI_NOOP; /* wait to be cancelled */ *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; - *cs++ = addr; + *cs++ = addr + 8; *cs++ = 0; /* cancel their spin as a compliment */ -- 2.27.0.rc2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx