On Wed, May 13, 2020 at 12:38:13PM +0300, Stanislav Lisovskiy wrote:
> Seems that only skl needs to have SAGV turned off
> for multipipe scenarios, so lets do it this way.
Commit msg still a bit misleading, but meh, pushed 1-3 anyway. Thanks.
>
> If anything blows up - we can always revert this patch.
>
> v2: Changed if condition to look better (Ville).
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++-----
> drivers/gpu/drm/i915/intel_pm.h | 3 ++-
> 2 files changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6a212d47aec8..de0f8cede59c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
<snip>
> @@ -3901,7 +3904,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> return ret;
> }
>
> - if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> + if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
I did wrap this line while applying since it was trivial and made
checkpatch happy.
I see one other valid checkpatch complaint in the report (some alignment
fail in one of the later patches). The wm debug >80col warnings we can't
really fix without some refactoring or making the code look evem uglier
so imo ignore those.
> ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index fd1dc422e6c5..614ac7f8d4cc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -42,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> struct skl_pipe_wm *out);
> void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> + const struct intel_bw_state *bw_state);
> int intel_enable_sagv(struct drm_i915_private *dev_priv);
> int intel_disable_sagv(struct drm_i915_private *dev_priv);
> void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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