>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Chris
>Wilson
>Sent: Wednesday, May 6, 2020 4:59 PM
>To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
>Subject: [PATCH 12/15] drm/i915: Replace the hardcoded
>I915_FENCE_TIMEOUT
>
>Expose the hardcoded timeout for unsignaled foreign fences as a Kconfig
>option, primarily to allow brave systems to disable the timeout and
>solely rely on correct signaling.
>
>Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
>Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
>---
> drivers/gpu/drm/i915/Kconfig.profile | 12 ++++++++++++
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
> drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_client_blt.c | 3 +--
> drivers/gpu/drm/i915/gem/i915_gem_fence.c | 4 ++--
> drivers/gpu/drm/i915/i915_config.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 10 +++++++++-
> drivers/gpu/drm/i915/i915_request.c | 9 ++++++---
> 9 files changed, 50 insertions(+), 11 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/i915_config.c
>
>diff --git a/drivers/gpu/drm/i915/Kconfig.profile
>b/drivers/gpu/drm/i915/Kconfig.profile
>index 0bfd276c19fe..3925be65d314 100644
>--- a/drivers/gpu/drm/i915/Kconfig.profile
>+++ b/drivers/gpu/drm/i915/Kconfig.profile
>@@ -1,3 +1,15 @@
>+config DRM_I915_FENCE_TIMEOUT
>+ int "Timeout for unsignaled foreign fences"
>+ default 10000 # milliseconds
>+ help
>+ When listening to a foreign fence, we install a supplementary timer
>+ to ensure that we are always signaled and our userspace is able to
>+ make forward progress. This value specifies the timeout used for an
>+ unsignaled foreign fence.
>+
>+ May be 0 to disable the timeout, and rely on the foreign fence being
>+ eventually signaled.
>+
> config DRM_I915_USERFAULT_AUTOSUSPEND
> int "Runtime autosuspend delay for userspace GGTT mmaps (ms)"
> default 250 # milliseconds
>diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>index 5359c736c789..b0da6ea6e3f1 100644
>--- a/drivers/gpu/drm/i915/Makefile
>+++ b/drivers/gpu/drm/i915/Makefile
>@@ -35,6 +35,7 @@ subdir-ccflags-y += -I$(srctree)/$(src)
>
> # core driver code
> i915-y += i915_drv.o \
>+ i915_config.o \
> i915_irq.o \
> i915_getparam.o \
> i915_params.o \
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index fd6d63b03489..432b4eeaf9f6 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -15814,7 +15814,7 @@ intel_prepare_plane_fb(struct drm_plane
>*_plane,
> if (new_plane_state->uapi.fence) { /* explicit fencing */
> ret = i915_sw_fence_await_dma_fence(&state-
>>commit_ready,
> new_plane_state-
>>uapi.fence,
>- I915_FENCE_TIMEOUT,
>+
>i915_fence_timeout(dev_priv),
> GFP_KERNEL);
> if (ret < 0)
> return ret;
>@@ -15841,7 +15841,8 @@ intel_prepare_plane_fb(struct drm_plane
>*_plane,
>
> ret = i915_sw_fence_await_reservation(&state-
>>commit_ready,
> obj->base.resv, NULL,
>- false,
>I915_FENCE_TIMEOUT,
>+ false,
>+
>i915_fence_timeout(dev_priv),
> GFP_KERNEL);
> if (ret < 0)
> goto unpin_fb;
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
>b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
>index 34be4c0ee7c5..bc0223716906 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
>@@ -108,7 +108,7 @@ bool i915_gem_clflush_object(struct
>drm_i915_gem_object *obj,
> if (clflush) {
> i915_sw_fence_await_reservation(&clflush->base.chain,
> obj->base.resv, NULL, true,
>- I915_FENCE_TIMEOUT,
>+
> i915_fence_timeout(to_i915(obj->base.dev)),
> I915_FENCE_GFP);
> dma_resv_add_excl_fence(obj->base.resv, &clflush-
>>base.dma);
> dma_fence_work_commit(&clflush->base);
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
>b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
>index 3a146aa2593b..d3a86a4d5c04 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
>@@ -288,8 +288,7 @@ int i915_gem_schedule_fill_pages_blt(struct
>drm_i915_gem_object *obj,
>
> i915_gem_object_lock(obj);
> err = i915_sw_fence_await_reservation(&work->wait,
>- obj->base.resv, NULL,
>- true, I915_FENCE_TIMEOUT,
>+ obj->base.resv, NULL, true, 0,
Did you miss this one, or is the '0' on purpose?
Mike
> I915_FENCE_GFP);
> if (err < 0) {
> dma_fence_set_error(&work->dma, err);
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_fence.c
>b/drivers/gpu/drm/i915/gem/i915_gem_fence.c
>index 2f6100ec2608..8ab842c80f99 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_fence.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_fence.c
>@@ -72,8 +72,8 @@ i915_gem_object_lock_fence(struct
>drm_i915_gem_object *obj)
> 0, 0);
>
> if (i915_sw_fence_await_reservation(&stub->chain,
>- obj->base.resv, NULL,
>- true, I915_FENCE_TIMEOUT,
>+ obj->base.resv, NULL, true,
>+ i915_fence_timeout(to_i915(obj-
>>base.dev)),
> I915_FENCE_GFP) < 0)
> goto err;
>
>diff --git a/drivers/gpu/drm/i915/i915_config.c
>b/drivers/gpu/drm/i915/i915_config.c
>new file mode 100644
>index 000000000000..b79b5f6d2cfa
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/i915_config.c
>@@ -0,0 +1,15 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2020 Intel Corporation
>+ */
>+
>+#include "i915_drv.h"
>+
>+unsigned long
>+i915_fence_context_timeout(const struct drm_i915_private *i915, u64
>context)
>+{
>+ if (context && IS_ACTIVE(CONFIG_DRM_I915_FENCE_TIMEOUT))
>+ return
>msecs_to_jiffies_timeout(CONFIG_DRM_I915_FENCE_TIMEOUT);
>+
>+ return 0;
>+}
>diff --git a/drivers/gpu/drm/i915/i915_drv.h
>b/drivers/gpu/drm/i915/i915_drv.h
>index 6af69555733e..2e3b5c4d0759 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -614,8 +614,16 @@ struct i915_gem_mm {
>
> #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
>
>+unsigned long i915_fence_context_timeout(const struct drm_i915_private
>*i915,
>+ u64 context);
>+
>+static inline unsigned long
>+i915_fence_timeout(const struct drm_i915_private *i915)
>+{
>+ return i915_fence_context_timeout(i915, U64_MAX);
>+}
>+
> #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
>-#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
>
> #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and
>subunits dead */
> #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active
>head */
>diff --git a/drivers/gpu/drm/i915/i915_request.c
>b/drivers/gpu/drm/i915/i915_request.c
>index fcf995e7d10c..304320afe32b 100644
>--- a/drivers/gpu/drm/i915/i915_request.c
>+++ b/drivers/gpu/drm/i915/i915_request.c
>@@ -1099,7 +1099,8 @@ i915_request_await_external(struct i915_request
>*rq, struct dma_fence *fence)
> {
> mark_external(rq);
> return i915_sw_fence_await_dma_fence(&rq->submit, fence,
>- fence->context ?
>I915_FENCE_TIMEOUT : 0,
>+ i915_fence_context_timeout(rq-
>>i915,
>+ fence-
>>context),
> I915_FENCE_GFP);
> }
>
>@@ -1230,7 +1231,8 @@ i915_request_await_proxy(struct i915_request *rq,
>struct dma_fence *fence)
> * Wait until we know the real fence so that can optimise the
> * inter-fence synchronisation.
> */
>- return __i915_request_await_proxy(rq, fence,
>I915_FENCE_TIMEOUT,
>+ return __i915_request_await_proxy(rq, fence,
>+ i915_fence_timeout(rq->i915),
> await_proxy, NULL);
> }
>
>@@ -1398,7 +1400,8 @@ i915_request_await_proxy_execution(struct
>i915_request *rq,
> * be able to hook into its execution, as opposed to waiting for
> * its completion.
> */
>- return __i915_request_await_proxy(rq, fence,
>I915_FENCE_TIMEOUT,
>+ return __i915_request_await_proxy(rq, fence,
>+ i915_fence_timeout(rq->i915),
> execution_proxy, hook);
> }
>
>--
>2.20.1
>
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