On Wed, Apr 15, 2020 at 12:33 PM Michel Dänzer <michel@xxxxxxxxxxx> wrote: > > On 2020-04-14 2:44 p.m., Daniel Vetter wrote: > > On Mon, Apr 13, 2020 at 10:08:07PM -0700, Manasi Navare wrote: > >> From: Bhanuprakash Modem <bhanuprakash.modem@xxxxxxxxx> > >> > >> [Why] > >> It's useful to know the min and max vrr range for IGT testing. > >> > >> [How] > >> Expose the min and max vfreq for the connector via a debugfs file > >> on the connector, "i915_vrr_info". > >> > >> Example usage: cat /sys/kernel/debug/dri/0/DP-1/i915_vrr_info > >> > >> v3: > >> * Remove the unnecessary debug print (Manasi) > >> v2: > >> * Fix the typo in max_vfreq (Manasi) > >> * Change the name of node to i915_vrr_info so we can add > >> other vrr info for more debug info (Manasi) > >> * Change the VRR capable to display Yes or No (Manasi) > >> * Fix indentation checkpatch errors (Manasi) > >> > >> Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@xxxxxxxxx> > >> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx> > >> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> > >> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > >> Tested-by: Manasi Navare <manasi.d.navare@xxxxxxxxx> > > > > So if I'm understanding things correctly AMD butchered the VRR stuff and > > only exposes it when: > > > > - VRR_ENABLED is set > > Not really surprising? :) > > > - _and_ you're using the legacy page_flip path, atomic flip doesn't > > support it > > Simon Ser has VRR working with sway using the atomic KMS API. > > > - _and_ the PAGE_FLIP_ASYNC flag is set. > > AFAIK it works both without and with PAGE_FLIP_ASYNC. (Async just means > tearing if the flip is programmed outside of vertical blank) Yeah Nicolas already explained it all on the igt thread, conclusion is that the igt needs some work to improve it (need to test the atomic path too, and try to be a bit less hackish with the timing tests). So all good, just me who panicked and got led astray by the comment in the igt and that amdgpu still implements its own page_flip callback (in completely separate paths, it doesn't seem to converge even in the low-level chip functions), so wasn't obvious to me from reading code that the atomic path would also work. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
