Quoting Matthew Auld (2020-03-31 16:07:21) > On Tue, 31 Mar 2020 at 13:42, Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote: > > > > When we allocate space in the GGTT we may have to allocate a larger > > region than will be populated by the object to accommodate fencing. Make > > sure that this space beyond the end of the buffer points safely into > > scratch space, in case the HW tries to access it anyway (e.g. fenced > > access to the last tile row). > > > > Reported-by: Imre Deak <imre.deak@xxxxxxxxx> > > References: https://gitlab.freedesktop.org/drm/intel/-/issues/1554 > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Matthew Auld <matthew.auld@xxxxxxxxx> > > Cc: Imre Deak <imre.deak@xxxxxxxxx> > > Cc: stable@xxxxxxxxxxxxxxx > > Do we not need similar treatment for gen6? It seems to also play > tricks with the nop clear range, or did we disable gen7 ppgtt in the > end? Currently disabled. But yes, if we use nop_clear_range we will need similar clearing. As this method turned out to be much easier than expected, I guess we should just do it anyway. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
