On Tue, 31 Mar 2020 at 13:42, Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote: > > When we allocate space in the GGTT we may have to allocate a larger > region than will be populated by the object to accommodate fencing. Make > sure that this space beyond the end of the buffer points safely into > scratch space, in case the HW tries to access it anyway (e.g. fenced > access to the last tile row). > > Reported-by: Imre Deak <imre.deak@xxxxxxxxx> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/1554 > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Matthew Auld <matthew.auld@xxxxxxxxx> > Cc: Imre Deak <imre.deak@xxxxxxxxx> > Cc: stable@xxxxxxxxxxxxxxx Do we not need similar treatment for gen6? It seems to also play tricks with the nop clear range, or did we disable gen7 ppgtt in the end? Reviewed-by: Matthew Auld <matthew.auld@xxxxxxxxx> _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
