Matt Roper <matthew.d.roper@xxxxxxxxx> writes: > The register this workaround updates is a render engine register in the > MCR range, so we should initialize this in rcs_engine_wa_init() rather > than gt_wa_init(). > > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1222 > Fixes: 36204d80bacb ("drm/i915/icl: Wa_1406680159") > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> At some sunny day mcr range verification might appear. Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 2318b55b9722..cbfc8d5ebb3e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -920,11 +920,6 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > SLICE_UNIT_LEVEL_CLKGATE, > MSCUNIT_CLKGATE_DIS); > > - /* Wa_1406680159:icl */ > - wa_write_or(wal, > - SUBSLICE_UNIT_LEVEL_CLKGATE, > - GWUNIT_CLKGATE_DIS); > - > /* Wa_1406838659:icl (pre-prod) */ > if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) > wa_write_or(wal, > @@ -1487,6 +1482,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > /* Wa_1407352427:icl,ehl */ > wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > PSDUNIT_CLKGATE_DIS); > + > + /* Wa_1406680159:icl,ehl */ > + wa_write_or(wal, > + SUBSLICE_UNIT_LEVEL_CLKGATE, > + GWUNIT_CLKGATE_DIS); > } > > if (IS_GEN_RANGE(i915, 9, 12)) { > -- > 2.24.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
