Relatively minor changes from v1: - Wa_1406306137:icl,ehl moves to the context workarounds rather than the engine workarounds. On gen11 the register we're updating is part of the render engine context (even though it isn't on gen12). - Dropped Wa_1409178092:icl,ehl again. Even with the WA implemented in the proper place and with all of the latest MCR programming updates this workaround still doesn't "stick." We'll have to seek guidance from the hardware team. - Swapped the order of the FBC address writes in Wa_1604278689:icl,ehl to ensure the "address valid" bit is turned off during the first write rather than the second. Mika noted that there's some internal evidence that we might only need to apply Wa_1207131216:icl,ehl when dealing with y-tiled surfaces, but we haven't received confirmation on that from the hardware team yet so I haven't changed the patch for that one at this time. Matt Roper (6): drm/i915: Handle all MCR ranges drm/i915: Add Wa_1207131216:icl,ehl drm/i915: Add Wa_1604278689:icl,ehl drm/i915: Add Wa_1406306137:icl,ehl drm/i915: Apply Wa_1406680159:icl,ehl as an engine workaround drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and EHL .../gpu/drm/i915/gem/i915_gem_object_blt.c | 14 ++++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++++++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 2 + 3 files changed, 59 insertions(+), 9 deletions(-) -- 2.24.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
