On Tue, Jan 28, 2020 at 03:37:06PM -0800, Matt Roper wrote:
> On Fri, Jan 24, 2020 at 10:44:56AM +0200, Stanislav Lisovskiy wrote:
> > During full modeset, global state(i.e dev_priv) is protected
> > by locking the crtcs in state, otherwise global state is not
> > serialized. Also if it is not a full modeset, we anyway
> > don't need to change DBuf slice configuration as Pipe configuration
> > doesn't change.
>
> Looks correct, but don't we need this earlier so that we don't have a
> bad bisection point in the git history (assuming we rely on this rather
> than the extra locking from the previous patch to cover the DC off
> race)?
Could perhaps just squash into the patch that moves these calls here.
Or move just after that patch in the series.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
>
> Matt
>
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 1c957df5c28c..888a9e94032e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15373,7 +15373,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > intel_encoders_update_prepare(state);
> >
> > /* Enable all new slices, we might need */
> > - icl_dbuf_slice_pre_update(state);
> > + if (state->modeset)
> > + icl_dbuf_slice_pre_update(state);
> >
> > /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> > dev_priv->display.commit_modeset_enables(state);
> > @@ -15432,7 +15433,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > }
> >
> > /* Disable all slices, we don't need */
> > - icl_dbuf_slice_post_update(state);
> > + if (state->modeset)
> > + icl_dbuf_slice_post_update(state);
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> > intel_post_plane_update(state, crtc);
> > --
> > 2.24.1.485.gad05a3d8e5
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
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