On Wed, Jan 29, 2020 at 06:32:04PM +0000, Chris Wilson wrote: > Quoting Ville Syrjala (2020-01-29 18:20:31) > > + intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), > > + DSB_ENABLE); > > + intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), > > + i915_ggtt_offset(dsb->vma)); > > intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), > > i915_ggtt_offset(dsb->vma) + tail); > > I still say this order looks dodgy for a ringbuffer. Is it all truly > latched by DSB_TAIL or might it start passing on being enabled and HEAD > != TAIL? My initial thoughts as well, but indeed it's the tail write that makes it go (or at least that's what the docs say). -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
