Quoting Ville Syrjala (2020-01-29 18:20:31) > + intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), > + DSB_ENABLE); > + intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), > + i915_ggtt_offset(dsb->vma)); > intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), > i915_ggtt_offset(dsb->vma) + tail); I still say this order looks dodgy for a ringbuffer. Is it all truly latched by DSB_TAIL or might it start passing on being enabled and HEAD != TAIL? -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
