Hi
2012/10/27 Daniel Vetter <daniel.vetter at ffwll.ch>:
> Atm we have a few funny issues where we enable/disable shared
> pll clocks. To make it clear that we are not required to enable/
> disable the pch plls together with the other pch resources (and
> so should keep it running when it's used by another pipe in
> a shared pll configuration) add a comment.
>
> This note is lifted from "Graphics BSpec: vol4g North Display Engine
> Registers [IVB], Display Mode Set Sequence", step 9.d. of the enable
> sequence:
>
> "Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be
> done anytime before enabling PCH transcoder)."
>
> Since fixing the pll sharing code to no longer disable shared plls
> if they're still in use is more involved, let's just stick with the
> comment for now.
>
> v2: Make the comment in the code clearer, to address questions raised
> by Paulo Zanoni in review.
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b19e3bb..bf2356c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3007,6 +3007,13 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> /* For PCH output, training FDI link */
> dev_priv->display.fdi_link_train(crtc);
>
> + /* XXX: pch pll's can be enabled any time before we enable the PCH
> + * transcoder, and we actually should do this to not upset any PCH
> + * transcoder that already use the clock when we share it.
> + *
> + * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
> + * unconditionally resets the pll - we need that to have the right LVDS
> + * enable sequence. */
> intel_enable_pch_pll(intel_crtc);
>
> if (HAS_PCH_LPT(dev)) {
> --
> 1.7.11.4
>
--
Paulo Zanoni
