Hi
2012/10/27 Daniel Vetter <daniel.vetter at ffwll.ch>:
> For reference, see "Graphics BSpec: vol4g North Display Engine
> Registers [IVB], Display Mode Set Sequence", step 4 of the enabling
> sequence:
>
> a. "Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency
> b. "Switch from Rawclk to PCDclk in FDI Receiver
> c. "Enable CPU FDI Transmitter PLL, wait for warmup"
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 90617cf..64f654c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3256,6 +3256,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> is_pch_port = intel_crtc_driving_pch(crtc);
>
> if (is_pch_port) {
> + /* Note: FDI PLL enabling _must_ be done before we enable the
> + * cpu pipes, hence this is separate from all the other fdi/pch
> + * enabling. */
> ironlake_fdi_pll_enable(intel_crtc);
> } else {
> assert_fdi_tx_disabled(dev_priv, pipe);
> --
> 1.7.11.4
>
--
Paulo Zanoni
