We need to set the timing override chicken bit after fdi link training
has completed and before we enable the dp transcoder. We also have to
clear that bit again after disabling the pch dp transcoder.
See "Graphics BSpec: vol4g North Display Engine Registers [IVB],
Display Mode Set Sequence" and "Graphics BSpec: vol4h South Display
Engine Registers [CPT, PPT], South Display Engine Transcoder and FDI
Control, Transcoder Debug and DFT, TRANS_CHICKEN_2" bit 31:
"Workaround : Enable the override prior to enabling the transcoder.
Disable the override after disabling the transcoder."
While at it, use the _PIPE macro for the other TRANS_DP register.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 8 +++++++-
drivers/gpu/drm/i915/intel_display.c | 15 ++++++++++++++-
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c7c4b96..84b09ee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4062,7 +4062,7 @@
#define TRANS_DP_CTL_A 0xe0300
#define TRANS_DP_CTL_B 0xe1300
#define TRANS_DP_CTL_C 0xe2300
-#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
+#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
#define TRANS_DP_OUTPUT_ENABLE (1<<31)
#define TRANS_DP_PORT_SEL_B (0<<29)
#define TRANS_DP_PORT_SEL_C (1<<29)
@@ -4082,6 +4082,12 @@
#define TRANS_DP_HSYNC_ACTIVE_LOW 0
#define TRANS_DP_SYNC_MASK (3<<3)
+#define TRANS_CHICKEN_2_A 0xf0064
+#define TRANS_CHICKEN_2_B 0xf1064
+#define TRANS_CHICKEN_2_C 0xf2064
+#define TRANS_CHICKEN_2(pipe) _PIPE(pipe, TRANS_CHICKEN_2_A, TRANS_CHICKEN_2_B)
+#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
+
/* SNB eDP training params */
/* SNB A-stepping */
#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index aa80ecb..8ab0fa5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2687,7 +2687,6 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
int pipe = intel_crtc->pipe;
u32 reg, temp;
-
/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
reg = FDI_RX_CTL(pipe);
temp = I915_READ(reg);
@@ -3060,6 +3059,14 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
+
+ /* Workaround: Set the timing override bit before enabling the
+ * DP pch transcoder. */
+ reg = TRANS_CHICKEN2(pipe);
+ temp = I915_READ(reg);
+ temp |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+ I915_WRITE(reg, temp);
+
reg = TRANS_DP_CTL(pipe);
temp = I915_READ(reg);
temp &= ~(TRANS_DP_PORT_SEL_MASK |
@@ -3365,6 +3372,12 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
BUG(); /* wtf */
}
I915_WRITE(PCH_DPLL_SEL, temp);
+
+ /* Workaround: Clear the timing override chicken bit again. */
+ reg = TRANS_CHICKEN2(pipe);
+ temp = I915_READ(reg);
+ temp &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
+ I915_WRITE(reg, temp);
}
/* disable PCH DPLL */
--
1.7.11.4
