On Thu, 25 Oct 2012 17:10:01 +0100, Damien Lespiau <damien.lespiau at gmail.com> wrote:
> From: Damien Lespiau <damien.lespiau at intel.com>
>
> HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
> register.
>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_sprite.c | 18 +++++++++++++-----
> 2 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index be22aeb..2a6c0b6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3187,6 +3187,7 @@
> #define _SPRA_SURF 0x7029c
> #define _SPRA_KEYMAX 0x702a0
> #define _SPRA_TILEOFF 0x702a4
> +#define _SPRA_OFFSET 0x702a4
> #define _SPRA_SCALE 0x70304
> #define SPRITE_SCALE_ENABLE (1<<31)
> #define SPRITE_FILTER_MASK (3<<29)
> @@ -3207,6 +3208,7 @@
> #define _SPRB_SURF 0x7129c
> #define _SPRB_KEYMAX 0x712a0
> #define _SPRB_TILEOFF 0x712a4
> +#define _SPRB_OFFSET 0x712a4
> #define _SPRB_SCALE 0x71304
> #define _SPRB_GAMC 0x71400
>
> @@ -3220,6 +3222,7 @@
> #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
> #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
> #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
> +#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
> #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
> #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 176c462..24b8231 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -127,13 +127,21 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
>
> I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
> I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> - if (obj->tiling_mode != I915_TILING_NONE) {
> - I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
> +
> + if (IS_HASWELL(dev)) {
> + /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single
> + * SPROFFSET register */
I don't know if upper layers sanitize already but
x should be < 8192 and y < 4096 in here, and both <4096 for ivb.
Emit warning and clamp if they are not in range?
> + I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
> } else {
> - unsigned long offset;
> + if (obj->tiling_mode != I915_TILING_NONE) {
> + I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
> + } else {
> + unsigned long offset;
>
> - offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
> - I915_WRITE(SPRLINOFF(pipe), offset);
> + offset = y * fb->pitches[0] +
> + x * (fb->bits_per_pixel / 8);
> + I915_WRITE(SPRLINOFF(pipe), offset);
> + }
> }
> I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> if (intel_plane->can_scale)
> --
> 1.7.7.5
Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>
