For Gen11+ platforms BSpec suggests disabling specific QGV points separately, depending on bandwidth limitations and current display configuration. Thus it required adding a new PCode request for disabling QGV points and some refactoring of already existing SAGV code. Stanislav Lisovskiy (2): drm/i915: Refactor intel_can_enable_sagv drm/i915: Restrict qgv points which don't have enough bandwidth. drivers/gpu/drm/i915/display/intel_atomic.c | 16 ++ drivers/gpu/drm/i915/display/intel_atomic.h | 3 + drivers/gpu/drm/i915/display/intel_bw.c | 105 ++++++-- drivers/gpu/drm/i915/display/intel_bw.h | 2 + drivers/gpu/drm/i915/display/intel_display.c | 58 ++++- .../drm/i915/display/intel_display_types.h | 11 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_pm.c | 228 +++++++++++++++++- 9 files changed, 394 insertions(+), 34 deletions(-) -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
