Quoting Mika Kuoppala (2019-10-15 16:44:41) > Add hdc pipeline flush to ensure memory state is coherent > in L3 when we are done. > > v2: Flush also in breadcrumbs (Chris) > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > --- > @@ -3416,7 +3417,9 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > PIPE_CONTROL_DEPTH_CACHE_FLUSH | > PIPE_CONTROL_DC_FLUSH_ENABLE | > - PIPE_CONTROL_FLUSH_ENABLE); > + PIPE_CONTROL_FLUSH_ENABLE | > + PIPE_CONTROL_HDC_PIPELINE_FLUSH); > + Bonus! -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
