Quoting Mika Kuoppala (2019-10-15 16:44:11) > Avoid possible hang in tsg,vfe units by keeping > l3 clocks runnings. > > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index ba65e5018978..81d299b27fbc 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -892,6 +892,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > wa_write_or(wal, > GAMT_CHKN_BIT_REG, > GAMT_CHKN_DISABLE_L3_COH_PIPE); > + > + /* Wa_1607087056:icl */ > + wa_write_or(wal, > + SLICE_UNIT_LEVEL_CLKGATE, > + L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); Seems to also impact tgl?. Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
