Quoting Mika Kuoppala (2019-10-11 14:39:11) > In order to ensure constant caches are invalidated > properly with a0, we need extra hdc flush after invalidation. > > References: HSDES#1604544889 > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 967e5b2e5e80..8db86772d8d4 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -3236,6 +3236,24 @@ static int gen12_emit_flush_render(struct i915_request *request, > > *cs++ = preparser_disable(false); > intel_ring_advance(request, cs); > + > + /* > + * Workaround constant cache invalidation issue > + * for tgl:a0, #1604544889 Do we have IS_TGL_REVID() yet? They should act as a reminder to remove them later. > + */ > + flags = 0; > + flags |= PIPE_CONTROL_CS_STALL; > + flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH; > + > + flags |= PIPE_CONTROL_STORE_DATA_INDEX; > + flags |= PIPE_CONTROL_QW_WRITE; Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
