== Series Details == Series: series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate URL : https://patchwork.freedesktop.org/series/67912/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9438571a7abe drm/i915/tgl: Include ro parts of l3 to invalidate -:21: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #21: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:233: +#define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */ ^ total: 0 errors, 0 warnings, 1 checks, 14 lines checked 8ed9c38c7c44 drm/i915/tgl: Add HDC Pipeline Flush -:19: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #19: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:235: +#define PIPE_CONTROL_HDC_PIPELINE_FLUSH (1<<9) /* gen 12 */ ^ total: 0 errors, 0 warnings, 1 checks, 14 lines checked 2855d8f17591 drm/i915/tgl: Add extra hdc flush workaround _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
