== Series Details == Series: TGL TC enabling (rev2) URL : https://patchwork.freedesktop.org/series/66695/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8a9f0a714a82 drm/i915/tgl: Add missing ddi clock select during DP init sequence b46c2208ba4d drm/i915/tgl: Finish modular FIA support on registers 11a14f2c9d45 drm/i915/tgl/pll: Set update_active_dpll 00109016e7c3 drm/i915/tgl: Add dkl phy registers d83006386e2a drm/i915/tgl: Add initial dkl pll support 143be4422b94 drm/i915/tgl: Add support for dkl pll write 1621e3c6980e drm/i915/tgl: TC helper function to return pin mapping f5c7aa23907a drm/i915/tgl: Add dkl phy programming sequences 38c47a4902ba drm/i915/icl: Unify disable and enable phy clock gating functions e39a78ba10d4 drm/i915/tgl: Check the UC health of tc controllers after power on 022a353b953d drm/i915/tgl: Add dkl phy pll calculations -:231: WARNING:LONG_LINE: line over 100 characters #231: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2852: + MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) | total: 0 errors, 1 warnings, 0 checks, 228 lines checked b1f9d61f9e63 drm/i915/tgl: Fix dkl link training 1b900733ba11 drm/i915/tgl: initialize TC and TBT ports _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
